1. Field of the Invention
The present invention relates to a semiconductor device having a test element, and a method of manufacturing the same, and more specifically to a semiconductor device having a test element group (TEG) for performing a check of a short circuit between storage nodes of memory cells stably, and a method of manufacturing the same.
2. Description of the Background Art
With high integration of devices, the size of chips is made smaller and the interval between storage nodes in semiconductor memory devices also becomes narrower. In a capacitor, a storage node made of polycrystal silicon whose surface is made rough is adopted to increase the capacity thereof. In the development of a dynamic random access memory (DRAM) having a chip size, a short circuit between storage nodes, resulting from a residue of the polycrystal silicon generated between the storage nodes, causes a serious problem of device-defectiveness. It is necessary to detect the short circuit early at the stage of examination using its TEG. Thus, the structure of the TEG making it possible to detect the short circuit between the storage nodes is required.
FIG. 14 is a sectional view which schematically illustrates the structure of a semiconductor device having a conventional TEG. FIG. 15 is a schematic sectional view taken along XVxe2x80x94XV line of FIG. 14.
Referring to FIGS. 14 and 15, the TEG for checking a short circuit between storage nodes has a structure similar to a memory cell array area (not illustrated). In the TEG, conductive layers 104 for word lines, corresponding to the word lines, and conductive layers 116 for bit lines, corresponding to the bit lines, are arranged to cross each other. Metal insulator semiconductor (MIS) transistors T are formed near the crossing sites. The MIS transistor T has a pair of source/drain areas 122, a gate insulating film 103, and a gate electrode 104.
The pair of source/drain areas 122 are formed on the surface, of a semiconductor substrate 101, separated electrically by a trench isolation 121 and at an interval from each other. The gate electrode 104 is formed through the gate insulating film 103 on the area sandwiched by the pair of source/drain areas 122. This gate electrode 104 has a polycrystal silicon film 104a into which an impurity is introduced (a doped polysilicon film 104a), and a tungsten silicide film 104b. 
A boro phospho tetra ethyl ortho silicate (BPTEOS) film 106 is formed to cover the MIS transistors T. Conductive layers 110 for storage nodes are formed on the BPTEOS film 106 to check a short circuit between the storage nodes.
The storage node conductive layers 110 are made into a thick-layer stack structure whose surface has coarse silicon crystal grains by depositing the doped polysilicon to have a thickness of 500 nm and then making the surface thereof rough. The storage node conductive layers 110 extend in one direction in parallel to the bit lines 116, and are electrically connected to the respective source/drain areas of the MIS transistors arranged along the above-mentioned direction.
A tetra ethyl ortho silicate (TEOS) interlayer dielectric 114 is formed on the storage node conductive layers 110. Aluminum interconnection layers 115 for connecting to pads for checking a short circuit between the storage nodes are formed on the TEOS interlayer dielectric 114. The aluminum interconnection layer 115 is connected to the storage node conductive layer 110 through a contact plug 113 made of tungsten. The storage node conductive layers 110, arranged in parallel, are alternately connected to the aluminum interconnection layers 115 that are different.
The respective voltages of the storage node conductive layers 110, which are alternately arranged, are measured through the pads for checking a short circuit, which are electrically to the aluminum interconnection layers 115, so that it can be checked whether any one of the storage nodes is short-circuited or not.
In the conventional thick-layer stack capacitor structure, its storage node conductive layers are composed of a thick film. Therefore, when etching is performed to make contact holes into which the contact plugs 113 are filled, it does not happen that the contact holes penetrate through the storage node conductive layers 110.
However, in order to obtain a capacitor having a large capacity, it is necessary to change the structure of the storage nodes from the thick-film stack type to a cylinder type and make the thickness of the storage node conductive layers as thin as 50 nm. In this case, contact holes into which the contact plugs 113 are filled penetrate through the storage node conductive layers when etching is performed to make the contact holes. As a result, it is feared that a short circuit between the contact plug 113, which is filled into the contact hole, and some other conductive layer beneath the storage node conductive layer, for example, the bit line, is caused. In this case, the contact area between the storage node conductive layer and the contact plug is reduced and further the contact plug and some other conductive layer are short-circuited. It is therefore impossible to detect a short circuit between the storage nodes stably.
An object of the present invention is to provide a semiconductor device having a test element which makes it possible to detect a short circuit between storage nodes stably even if the shape of the storage nodes is made cylindrical, and a method of manufacturing the same.
The semiconductor device having a test element of the present invention is a semiconductor device having the test element for testing whether respective cylinder type electrodes in capacitors are short-circuited or not, wherein the test element includes the test conductive layer, the conductive area for leading, and a interconnection layer. The test conductive layer is produced by the same step for producing the cylinder type electrodes, and has a cylinder-shaped portion. The leading conductive area is positioned below the test conductive layer and is electrically connected to the test conductive layer. The interconnection layer is positioned above the test conductive layer, and is electrically connected to the leading conductive area to give a test signal for checking the short-circuit through the leading conductive area to the test conductive layer.
According to the semiconductor device having the test element, the interconnection layer above the test conductive layer is not directly connected to the test conductive layer but is connected through the leading conductive area below the test conductive layer to the test conductive layer. Therefore, it does not happen that contacts dropped from the interconnection layer to the test conductive layer penetrate through the test conductive layer so that a short circuit between the contacts and some other conductive layer is caused. Thus, a short circuit between storage nodes can be stably detected.
Preferably, the semiconductor device of the present invention further includes a leading interconnection layer that is positioned between the leading conductive area and the interconnection layer and is electrically connected to both of the leading conductive area and the interconnection layer. This leading interconnection layer is made of a material that is less easily etched than the test conductive layer under etching conditions for making a contact hole for connecting the leading interconnection layer and the interconnection layer.
In this manner, it is prevented that the contacts dropped from the interconnection layer to the leading interconnection layer penetrate through the leading interconnection layer so that a short circuit between the contacts and some other conductive layer is caused.
Preferably, the semiconductor device of the present invention further includes a semiconductor substrate, and the leading conductive area is a linear impurity region formed in the semiconductor substrate.
In this manner, the impurity region is used to make it possible to detect a short circuit between the storage nodes stably.
Preferably, the semiconductor device of the present invention further includes a semiconductor substrate, and the leading conductive area is a linear conductive layer formed on a surface of the semiconductor substrate.
In this manner, the conductive layer is used to make it possible to detect a short circuit between the storage nodes stably.
Preferably, in the semiconductor device of the present invention, each of the capacitors and an insulated gate type field effect transistor constitute a memory cell, and the leading conductive area is a gate conductive layer that is produced by the same step for producing a gate electrode of the insulated gate type field effect transistor.
In this manner, the gate conductive layer is used to make it possible to detect a short circuit between the storage nodes stably.
The method of the present invention is a method of manufacturing a semiconductor device including a plurality of memory cells, each of which includes a capacitor and an insulated gate type field effect transistor, and a test element for testing whether respective cylinder type electrodes of the capacitors are short-circuited or not, including the steps of forming a gate conductive layer of the test element at the same time of forming a gate electrode of the insulated gate type field effect transistor; forming an insulating layer covering the periphery of the gate conductive layer; removing an upper portion of the insulating layer to expose the gate conductive layer from the insulating layer; forming a test conductive layer of the test element to be electrically connected to a exposed portion of the gate conductive layer at the same time of forming the cylinder type electrodes of the capacitors; and forming a interconnection layer for giving a test signal for checking the short circuit through the gate conductive layer to the test conductive layer above the test conductive layer to be electrically connected to the exposed portion of the gate conductive layer.
According to the process for producing the semiconductor device having the test element, the gate conductive layer is also used as leading wiring so that the step of producing the leading wiring separately is unnecessary and the manufacturing process can be made simple.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.